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june 2009 rev 3 1/46 1 stw4511 7-channel power management unit features 2 step-down converters vsdc1: 1 v to 1.5 v ? 600 ma maximum output current ? i2c control possibility ? programmable default output voltage (1.45 v predefined value (a) ) ? off mode on external pwren signal vsdc2: 1.8 v ? 600 ma maximum output current ? off mode on external pwren signal 5 low-drop output regulators vdig: 1.0 v (100 ma) to 1.5 v - 250 ma max ? match up vsdc1 output voltage ? always switched on after start-up (even on reset) vana1: 1.8 v - 150 ma max ? match up vsdc2 output voltage ? always switched on after start-up (even on reset) vana2/3/4: 1.8, 2.5, 2.8, 3.3 v - 150 ma max ? on or off mode possibility at start-up ? on/off mode controlled by i2c or by pwren = 0 battery supervisor programmable minimum battery level power supply switches 2 internal switches for external dram memory supply (1.8 v) supply via vana1 in low power mode supply via vsdc2 in high power mode miscellaneous i2c control temperature shutdown internal clock generation for supply switching and state machine sequencing application portable navigation device (gps) portable multimedia player personal digital assistant (pda) portable consumer equipment or handheld devices description stw4511 is a 7-channel power management device developed for applications powered by one li-ion or li-polymer cell. stw4511 embeds 2 highly efficient step-down dc/dc converters and 5 ldo regulators. stw4511 enables two always- on ldos for low system quiescent current. integrated switches are used to keep the dram memories supplied even in stand by mode. a. this value can be one of the available output voltages (see power control register @ 05h) - please contact st-ericsson sales if different predefined output voltage is needed. 7)%*$ [[pp edoovpp tfga, 64 balls, 6 mm x 6 mm x 1.2 mm with 0.5mm pitch www.stericsson.com
contents stw4511 2/46 contents 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.1 package ball map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.2 ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 stw4511 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 high power mode (hpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 low power mode (lpm) or sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 battery supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 ram memory supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6.1 1.8v switch definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6.2 shipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6.3 1.8 v switch electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 control pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8 power supply timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.9 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9.1 step-down converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9.2 ldo regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.10 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.1 step-down converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 low-drop output converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.3 dc/dc converter monitoring characteristics . . . . . . . . . . . . . . . . . . . . . 28 3.3 digital specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 cmos input/output static characteristics: i2c interface . . . . . . . . . . . . . 28 3.3.2 cmos input/output dynamic characteristics: i2c interface . . . . . . . . . . 29 3.3.3 cmos input/output static characteristics: vddio level . . . . . . . . . . . . . 29
stw4511 contents 3/46 3.3.4 cmos input static characteristics: vbat level . . . . . . . . . . . . . . . . . . . . 30 3.3.5 nmos input pon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 internal 32 khz clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 application and external components . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 register definition and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of tables stw4511 4/46 list of tables table 1. package ball out for tfbga 64 - 6 mm x 6 mm with 0.5 mm pitch . . . . . . . . . . . . . . . . . . . 7 table 2. ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. battery voltage falling threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. battery voltage rising threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. vswitch truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. supplies thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. vsdc1 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. vsdc2 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. vana1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. vana2/3/4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. vdig electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. vsdc1/2 monitoring output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. cmos input/output static characteristics: i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. cmos input/output dynamic characteristics: i2c interface. . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18. vddio level: control i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. cmos input static characteristics: vbat level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 20. pon input static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 21. device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22. register address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 23. register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 24. list of materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 25. register general information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 26. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 27. power control register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 28. tfbga 6mm x 6mm x 1.2mm with 0.5 mm pitch and 0.3 mm ball. . . . . . . . . . . . . . . . . . . 43 table 29. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
stw4511 list of figures 5/46 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 1.8v switch diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. initial start up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. low power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. wake-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. device power off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. control interface: i2c format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. control interface: i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10. tfbga 6mm x 6mm x 1.2mm with 0.5 mm pitch and 0.3 mm ball. . . . . . . . . . . . . . . . . . . 44
product overview stw4511 6/46 1 product overview the stw4511 device is a power management unit (pmu) that integrates: two step down converters, five ldos, among which two are always switched on, ram supply in low power mode, autonomous state machine handling smooth supply sequencing, die temperature shutdown, battery supervisor with programmable minimum battery voltage and processor reset. 1.1 block diagram figure 1. block diagram pmic bias & ref soft-start smps monitoring ldo vana1 vref18 vdig vbat_vdig vana1 vbat_vana1_vana3 vana3 ldo vana3 ldo vdig ldo vana2 ldo vana4 vana2 vbat_vana2 vana4 vbat_vana4 scl voltage supply selection vana2-sel_0 vana2-sel_1 vana4-sel_0 vana4-sel_1 vana3-sel_0 vana3-sel_1 internal osc smps vsdc1 vsdc1_vbat vsdc1_vlx vsdc1_gnd vsdc1_fb smps vsdc2 vsdc2_vbat vsdc2_vlx vsdc2_gnd vsdc2-fb sw-reset general control pwren vddok pon res_pro i2c clock & control pmic thsd gnd sda vbat_ana vbat_dig battery supervisor vbat_max_thr_0 vbat_max_thr_1 vbat_min_thr_0 vbat_min_thr_1 vbat_thr_sel vram_in 1.8v switch vram_out vram-sel vddio
stw4511 product overview 7/46 1.2 ball information 1.2.1 package ball map 1.2.2 ball description the device includes four ball types: vddd/vdda: digital/analog positive supply gndd/gnda: digital/analog ground do/di/dio: digital output/input/input-output ao/ai/aio: analog output/input/input-output table 1. package ball out for tfbga 64 - 6 mm x 6 mm with 0.5 mm pitch 12345678910 a reserved vsdc2_gnd vsdc2_vlx vsdc2_vbat gnd_ana vdig vana1 vbat_ vana1_ vana3 vana3 vref18 b reserved vsdc2_gnd vsdc2_vlx vsdc2_vbat vsdc2_fb vbat_ana vbat_vdig not used reserved pon c gnd_dig reserved reserved vsdc1_fb d vbat_dig reserved vsdc1_gnd vsdc1_gnd e vram_in reserved vsdc1_vlx vsdc1_vlx f vram_out reserved vsdc1_vbat vsdc1_vbat g vram_sel vana4_ sel_0 vbat_min_ thr_0 vana2 h vddok not used not used vbat- vana2 j res_pro not used not used vana4_ sel_1 pwren vana2_ sel_0 vana3_ sel_0 vbat_max_ thr_0 not used vddio k sw_reset vbat_ vana4 vana4 scl sda vbat_thr_ sel vana2_ sel_1 vana3_ sel_1 vbat_max_ thr_1 vbat_min_ thr_1 table 2. ball description ball number name type description step-down converters f9, f10 vsdc1_ vbat vdda smps dedicated supply input e9, e10 vsdc1_vlx ao smps coil output c10 vsdc1_fb ai smps feedback d9, d10 vsdc1_gnd gnda smps dedicated ground a4, b4 vsdc2_ vbat vdda smps dedicated supply input a3, b3 vsdc2_vlx ao smps coil output b5 vsdc2_fb ai smps feedback a2, b2 vsdc2_gnd gnda smps dedicated ground 14 switched converters total ball number
product overview stw4511 8/46 ldo converters a8 vbat_vana1_vana3 vdda ldo dedicated supply input a7 vana1 ao ldo output h10 vbat_vana2 vdda ldo dedicated supply input g10 vana2 ao ldo output a9 vana3 ao ldo output b7 vbat_vdig vdda ldo dedicated supply input a6 vdig ao ldo output k2 vbat_vana4 vdda ldo dedicated supply input k3 vana4 ao ldo output 9 linear converter total ball number i2c interface k5 sda di/o (1.8v) i2c data interface k4 scl di (1.8v) i2c clock interface 2 control interface ball number general control for power supplies b10 pon di (nmos) pull- down 1.5 m power on of the supplies part h1 vddok do (1.8v) smps high value monitoring status j1 res_pro do (1.8v) processor reset j5 pwren di (1.8v) pull-up 1.5m sleep high power mode/low power mode control k1 sw_reset di (1.8v) pull-up 1.5m s/w reset from processor 5 pmic general control total ball number selection voltage inputs j6 vana2-sel_0 di (vbat) voltage selection k7 vana2_sel_1 di (vbat) voltage selection j7 vana3_sel_0 di (vbat) voltage selection k8 vana3_sel_1 di (vbat) voltage selection g2 vana4_sel_0 di (vbat) voltage selection j4 vana4_sel_1 di (vbat) voltage selection g9 vbat_min_thr_0 di (vbat) battery voltage threshold to set the processor in reset table 2. ball description (continued) ball number name type description
stw4511 product overview 9/46 k10 vbat_min_thr_1 di (vbat) battery voltage threshold to set the processor in reset j8 vbat_max_thr_0 di (vbat) battery voltage threshold to set the processor in hpm k9 vbat_max_thr_1 di (vbat) battery voltage threshold to set the processor in hpm 10 total voltage selection inputs other inputs and outputs a10 vref18 ao internal reference of the power management device j10 vddio di io power supply b6 vbat-ana vdda pm analog part supply d1 vbat-dig vddd oscillator part supply k6 vbat_thr_sel di (vbat) battery voltage supervision enable c1 gnd_dig gndd ground a5 gnd_ana gnda ground e1 vram_in ai 1.8v switch input from vsdc2 for memory f1 vram_out ao 1.8v output g1 vram_sel di (vbat) memory supply switch enable. d2 reserved opened test purpose e2 reserved opened test purpose f2 reserved opened test purpose b9 reserved opened test purpose a1 reserved gnda test purpose b1 reserved gnda test purpose c2 reserved gnda test purpose c9 reserved gnda test purpose 16 other i/o ball number not used balls b8, h2, j2, j3, h9, j9 not used opened 6 not used 64 overall ball number table 2. ball description (continued) ball number name type description
stw4511 description stw4511 10/46 2 stw4511 description 2.1 introduction the device integrates power supplies for the processor and associated peripherals. 2.2 power on the device is in power on mode when pon is set to 1 (pon = 1). power on state is also reached by connecting directly the input pin to vbat or to a voltage above 1 v. when pon equals 0 (pon = 0) the device completely shuts down. thus, it is possible to make a full hard reset of the supplies. 2.3 high power mode (hpm) the device is in high power mode (hpm) when pwren is set to 1 (pwren = 1). the converter outputs are then regulated and able to supply the dedicated application features. at power on the device must be in high power mode. for that purpose, the ic includes an internal pull-up on the pwren ball. 2.4 low power mode (lpm) or sleep mode the device is in sleep mode when pwren is set to 0 (pwren = 0). vana1 and vdig signal values do not change. the two step-down converters are switched off. the overall consumption is then reduced to leakage current. vana2, vana3, and vana4 are switched off if vana2_vana3_off = 1 and vana4_off = 1 (see power control register @ 09h ). in other cases, vana2, vana3, and vana4 remain in high power mode. 2.5 battery supervisor stw4511 has two different battery voltage thresholds: battery voltage falling threshold: when the battery voltage drops down below this threshold, the device shuts down battery voltage rising threshold: when the battery voltage rises above this threshold, the device can (re-)start in high- power mode if pon is set to 1 (pon=1). the battery supervisor feature is enabled when vbat_thr_sel ball is set to 1 (vbat_thr_sel = 1). low threshold values stop the device when the battery is very low. the battery supervisor falling/rising thresholds are programmable via dedicated signals, vbat_min_thr_0/1 and vbat_max_thr_0/1 respectively. these pins can be connected either to the battery voltage or to ground.
stw4511 stw4511 description 11/46 the rising threshold ensures that the battery has enough energy to supply the whole application at start up. the device starts when the battery supply rises above the threshold rising value. below the falling down threshold the battery has not enough energy to supply the always-on parts, the device is completely switched off. 2.6 ram memory supply 2.6.1 1.8v switch definition stw4511 includes integrated switches that supply the dram memory with 1.8 v always-on supply in low power mode and, with 1.8 v supply from the step-down converter in high power mode. the vram_out ball supplies the dram memory. the vram_sel connected to the battery voltage enables the ram memory supply. vram_sel is active high. vsdc2 output is connected to the vram_in ball. an internal switch connects this input to the vram_out. this switch is closed only in high power mode. an internal switch connects the vana1 output (internal connection, no ball used) to the vram_out. this switch is closed only in low power mode, when pwren signal is low. when pon is low, the vram_out is switched to ground via the use of a third internal switch. table 3. battery voltage falling threshold vbat_min_thr0 vbat_min_thr1 vbat-thr-en threshold value (v) 0012.7 0112.85 1013.05 1113.3 xx02.25 table 4. battery voltage rising threshold vbat_max_thr0 vbat_max_thr1 vbat-thr-en threshold value (v) 0013.4 0113.5 1013.6 1113.7 xx02.65
stw4511 description stw4511 12/46 figure 2. 1.8v switch diagram 2.6.2 shipping mode shipping mode is a special feature that can be programmed using the bit 2 of application register 2 @ 11h. this bit controls the shipping mode feature that can force switches s1 and s2 to be opened. the ram is not supplied. this mode permits to limit the ram consumption when the device is moved from the factory to the end-user. 2.6.3 1.8 v switch electrical characteristics vsdc2 @ 1.8v control vana1 @ 1.8v vram_in vram_out vana1 s1 s2 vsdc2 table 5. vswitch truth table pwren vram_sel shipping mode 11h bit2 vram_out 1 0 0 gnd 1 1 0 vsdc2 1 0 1 gnd 1 1 1 gnd 0 0 0 gnd 0 1 0 vana1 0 0 1 gnd 0 1 1 gnd table 6. electrical characteristics parameter condition min. typ. max. unit vram input voltage -3% 1.8 +3% v vram output voltage 1.70 1.8 +3% v
stw4511 stw4511 description 13/46 s1_i_max maximum current through the switch in hpm 140 ma s2_i_max maximum current through the switch in lpm 0.3 ma s1 ron voltage = 1.8v 0.2 s2 ron voltage = 1.8v @ vbat=3.6v 0.08 1 k table 6. electrical characteristics parameter condition min. typ. max. unit
stw4511 description stw4511 14/46 2.7 control pin description control pin pon pon input signal is active high. pon signal is used to turn on the device and start the internal state machine that handles the supply sequencing. pon ball can be directly connected to the battery voltage. pon voltage must always be lower or equal to vbat. control pin pwren pwren input signal is active high. pwren signal sets the device in high power mode. at start up the pwren signal is masked until the internal oscillator stabilizes and the device is biased. after this period, pwren is handled by the device internal state machine. when pwren = 0 (low power mode): vsdc1 and vsdc2 are switched off vana1 and vdig remain in hpm vana2/3/4 are switched off, but can remain in hpm ( power control register @ 09h - vana2/3_off and vana4_off) when pwren is not driven by external components (typically at start-up), an internal pull-up ties pwren to high level to ensure power on in high power mode. control pin res_pro res_pro is an output signal used to reset the processor. res_pro is active low. res_pro = 0 when: the device is starting up, when the battery voltage drops below the battery voltage threshold programmed by the battery supervisor control pin vddok vddok is an output signal pin active high. vddok confirms that vsdc1, vsdc2 values are within the output voltage range. vddok falls to 0 when: pwren = 0 vsdc1 or vsdc2 values are below the defined threshold (output voltage monitoring), see ta b l e 1 6 in chapter 3: electrical characteristics . the battery voltage drops below the battery voltage threshold programmed by the battery supervisor control pin sw-reset this input signal is used to reset all registers except the ones at 1eh and 1fh addresses. sw-reset signal is active low.
stw4511 stw4511 description 15/46 2.8 power supply timing diagrams start up sequence when pon = 1 vana1 and vdig are switched on, these ldo remain on until they are reset by pon = 0. when pon = 1 and pwren = 1 vsdc2 and vsdc1 are switched on only if vana1 and vdig have also been switched on, vana2, vana3, vana4 can start up simultaneously to supply the peripherals. alternatively, vana2, vana3, vana4 can be off at start up and then controlled by i2c ( power control register @ 07h - en_vana3, en_vana4 and power control register @ 08h - en_vana2) vana2, vana3 and vana4 are switched on at the same time as vsdc2 when res_pro = 1 the processor is out of reset mode and the application is running.
stw4511 description stw4511 16/46 figure 3. initial start up sequence ,qwb3rq ,qwhuqdobrvf 'hylfhlqwhuqdo vwduwxs 3gqbuhjxodwru lqwvljqdo 9gg2. ,qwb&orfn. 5(6(7 5hvbsur ,&ri30,&dydlodeoh 3zuhq 9glj#vdphyrowdjhdv9vgf 9vgf#9 9dqd#9 :khqfrqwuroohge\3rq3zuhq9dqd #9wr9 9rxwdozd\v 21 3:5(1lqwhuqdoo\pdvnhg 3urfhvvrulqdfwlyhvwdwh 9vgf#wr9 !pv 9rxwiru shulskhudov 3urfhvvru 9rxw3rzhu 9%dw 9edwbpd[bwku 9edwbplqbwku 3rq 5hvbsurlqkljklpshgdqfh
stw4511 stw4511 description 17/46 lpm mode sequence when pwren = 0 vsdc1 and vsdc2 are switched off vana1 and vdig remain in hpm vana2/3/4 can be in off mode or stay in hpm ( power control register @ 09h - vana2/3_off, vana4_off) figure 4. low power sequence 3rq 9gg2. ,qwb&orfn. 5hvbsur 3zuhq 9glj#vdphyrowdjhdv9vgf 9vgf#9 9dqd#9 9dqd#9wr9 9rxwdozd\v 21 3:5(1lqwhuqdoo\ pdvnhg 9vgf#wr9 9rxwiru shulskhudov 3urfhvvru 9rxw3rzhu 9%dw 9edwbpd[bwku 9edwbplqbwku ,qwb3rq
stw4511 description stw4511 18/46 wake-up sequence the wake-up sequence occurs when pwren goes from 0 to 1: vana1 and vdig stay in hpm vsdc2 and vsdc1 are switched on vana2/3/4 are switched off or stay in hpm ( power control register @ 09h - vana2/3_off, vana4_off). figure 5. wake-up sequence 3rq 9gg2. ,qwb&orfn. 5hvbsur 3zuhq 9glj#6dph9vgfyrowdjh 9vgf#9 9dqd#9 9dqd#wr9 9rxwdozd\v 21 3:5(1lqwhuqdoo\ pdvnhg 9vgf#wr9 9rxwiru shulskhudov 3urfhvvru 9rxw3rzhu 9%dw 9edwbpd[bwku 9edwbplqbwku ,qwb3rq
stw4511 stw4511 description 19/46 device power-off sequence the device power-off sequence occurs when the battery voltage falls under the vbat-min-thr battery voltage threshold: all power supplies are turned off, a s/w threshold can be added to switch off the dc/dc converter before the low battery threshold is reached. this is a smart way to keep only the always-on ldo and let the processor in sleep mode. the application quickly restarts when an external power supply is plugged. figure 6. device power off sequence 9%dw 9gg2. ,qwb&orfn. 5hvbsur 3zuhq 9glj#6dph 9vgfyrowdjh 9vgf#9 9dqd#9 9dqd#9wr9 9rxwdozd\v 21 9vgf# wr9 9rxwiru shulskhudov 9rxw3rzhu 30,&vwrsshg 1hz,qlwldosrzhu21vhtxhqfh ,qwb3rq 9edwbplqbwku 9edwbpd[bwku
stw4511 description stw4511 20/46 2.9 power supplies the device has 2 step-down converters and 5 ldo supplies. 2.9.1 step-down converters vsdc1 dc/dc converter supply voltage vsdc1 is a step-down converter with a very high efficiency. adjustable voltage levels enable a dynamic scaling voltage suitable for any supply voltage with cmos process. vsdc1 has 2 modes: high power mode (hpm) to supply the application low power mode (lpm) to switch off the output voltage. the regulated output voltage levels are adjustable by controlling the dedicated registers via i2c interface ( power control register @ 05h ). the output voltage has predefined values at start-up which can be chosen in the available range defined in the power control register @ 05h (see note 1 ). the output voltage is coupled with the ldo vdig to ensure the same output voltage values at both outputs. the power supply is switched off by pwren signal set low level and is switched on by pwren signal set high. note: 1 for any other default output voltages, please contact your local st-ericsson sales. vsdc2 dc/dc converter supply voltage vsdc2 is a step-down converter with a very high efficiency. 1.8 v voltage level enables to supply all i/o voltages or any other voltage requested by the application. vsdc2 has 2 modes: high power mode (hpm) to supply the application, low power mode (lpm) to switch off the output voltage. the power supply is switched off by pwren signal set low and is switched on by pwren signal set high. 2.9.2 ldo regulators vdig ldo regulator vdig ldo regulator has the same adjustment levels as vsdc1. vdig is switched on at start-up and remains on when the application is power supplied. output voltage levels are adjustable via the vsdc1 dedicated registers. vana1 ldo regulator vana1 is a ldo regulator with 1.8 v output voltage level.
stw4511 stw4511 description 21/46 vana1 is switched on at start-up and remains always on when the application is power supplied. vana2, vana3,vana4 ldo regulators vana2, vana3 and vana4 are adjustable ldo regulators with four output voltage levels used to supply different application peripherals. vana2/3/4 are turned on after pon = 1 and pwren =1, in that case the three power supplies are controlled by en_vana(i) bit set high by default ( note 1 ) - power control register @ 07h , en_vana3, en_vana4 and power control register @ 08h - en_vana2. if vana2/3/4 need to be controlled directly by i2c, the converters are controlled by pdn_vana(i) bit in application controls register 1 @ 10h - pdn_vana2 and application controls register 2 @ 11h - pdn_vana3, pdn_vana4. the pdn_vana(i) bit and en_vana(i) control bit are or-gated features. vana2/3/4 high and low power modes are enabled by register power control register @ 09h - vana2/3_off, vana4_off ( note 1 ). output voltage levels are adjustable by connecting the dedicated pins vana2/3/4 _ sel_0 and vana2/3/4_sel_1 to battery voltage or to the ground. note: 1 for the different possible configurations of the vana(i) supplies, please contact directly your st-ericsson sales office. table 7. selection table vana(i)_sel_1 vana(i)_sel_0 output voltage (v) 001.8 012.5 102.8 113.3
stw4511 description stw4511 22/46 2.10 thermal shutdown a thermal sensor monitors the device temperature. this sensor is placed near the hottest part of the device. when the temperature exceeds the thermal threshold, the supplies are turned off. the supplies are turned back to their default start-up state, starting on pon = 1, after around 10 ms (device at room temperature (25c). the device mode changes back to normal and is ready to be controlled by i2c. table 8. supplies thermal shutdown description min. typ. max. unit supply thermal threshold 150 c
stw4511 electrical characteristics 23/46 3 electrical characteristics otherwise specified typical electrical characteristics have been defined for 25c ambient temperature and 3.6 v battery voltage. 3.1 absolute maximum rating table 9. absolute maximum ratings parameter condition min. typ. max. unit input supply operating voltage 2.7 3.6 5.5 v input supply maximum rating voltage 2.7 7 v vddio rating voltage 1.65 1.8 1.84 v operating temperature -40 +85 c junction operating temperature spec. is guaranteed up to 125c +125 c junction rating temperature +150 c consumption in off mode (pon = 0) vbat = 3.6 v 10 a consumption in sleep mode at 25c, vbat = 3.6v pon = 1 and pwren = 0 180 a esd hbm jesd22-a114-b -2 +2 kv cdm ansi-esdsm5.3.1-1999 -450 +500 v package rth 70 c/w
electrical characteristics stw4511 24/46 3.2 electrical characteristics 3.2.1 step-down converters 1. guaranteed by design 2. quiescent current defined as the current measured on the vsdc1 dedicated power supply table 10. vsdc1 electrical characteristics parameter name condition min. typ. max. unit vsupply 2.7 5.5 v output voltage 16 steps -5% 1.0 to 1.5 +5% v vripple output voltage ripple 10 mvpp output load current 0 600 ma efficiency 86 % short circuit limitation (1) 0.9 1.2 1.4 a quiescent current (2) 5a power-down current 1.5 a switching frequency 900 khz psrr (1) 1khz < f < 10khz 40 db rising slope iout = 10ma 0.3 ms/v line regulation vbat [2.7, 5.5v] 10 mv load regulation iout [0.1, 600ma] 10 mv line transient (1) vsdc1 = 1.2v iout = 200ma vbat = 300mv tr = tf = 10s 7mv load transient (1) vsdc1 = 1.2v iout = [1, 400ma] tr = tf = 100ns 70 mv
stw4511 electrical characteristics 25/46 1. guaranteed by design 2. quiescent current defined as the current measured on the vsdc2 dedicated power supply table 11. vsdc2 electrical characteristics parameter name condition min. typ. max. unit vsupply 2.7 5.5 v output voltage 3% 1.8 +3% v vripple output voltage ripple 10 mvpp output load current 0 600 ma efficiency 90 % short circuit limitation (1) 0.9 1.2 1.4 a quiescent current (2) 5a power-down current 1.5 a switching frequency 900 khz psrr (1) 1khz < f < 10khz 40 db rising time (10 to 90%) 0.5 ms line regulation vbat [2.7, 5.5v] 10 mv load regulation iout [0.1, 600ma] 10 mv line transient (1) vsdc2 = 1.8v iout = 200ma vbat = 300mv tr = tf = 10s 7mv load transient (1) vsdc2 = 1.8v iout = [1, 400ma] tr = tf = 100ns 70 mv
electrical characteristics stw4511 26/46 3.2.2 low-drop output converters 1. guaranteed by design 2. quiescent current defined as the current measured on the vana1 dedicated power supply table 12. vana1 electrical characteristics parameter name condition min. typ. max. unit vsupply 2.7 5.5 v output voltage -3% 1.8 +3% v output load current 150 ma short circuit limitation (1) 230 340 550 ma quiescent current (2) no load 30 a power-down current 1 a power supply rejection (1) f < 20khz f < 100khz 50 45 db rising time (10 to 90%) output voltage 1.8v iout = 10ma 0.5 ms line regulation vbat [2.7, 5.5v] 5 mv load regulation iout [0.1, 150ma] 10 mv line transient (1) vana1= 1.8v iout = 150ma vbat = 300mv tr = tf = 10s 2mv load transient (1) vsdc2 = 1.8v iout = [1, 150ma] tr = tf = 1s 20 mv table 13. vana2/3/4 electrical characteristics parameter name condition min. typ. max. unit vsupply max[vana(i)+0.2v, vbat_min] 5.5 v output voltage -3% 1.8 2.5 2.8 3.3 +3% v output load current 150 ma short circuit limitation (1) 230 340 550 ma quiescent current (2) no load 30 a power-down current 1 a power supply rejection (1) f < 20khz f < 100khz 50 45 db
stw4511 electrical characteristics 27/46 rising slope for vana4 20 s/v rising slope for vana2, vana3 iout = 10ma 0.3 ms/v line regulation vbat [2.7, 5.5v] 5 mv load regulation iout [0.1, 150ma] 10 mv line transient (1) vana1= 2.8v iout = 150ma vbat = 300mv tr = tf = 10s 2mv load regulation (1) vsdc2 = 1.8v iout = [1, 150ma] tr = tf = 1s 20 mv 1. guaranteed by design 2. quiescent current defined as the current measured on the vana2/3 dedicated power supply table 14. vdig electrical characteristics parameter name condition min. typ. max. unit vsupply 2.7 5.5 v output voltage -3% 1.0 to 1.5 +3% v output load current 250 ma short circuit limitation (1) 1. guaranteed by design 330 800 ma quiescent current (2) 2. quiescent current defined as the current measured on the vdig dedicated power supply no load 43 a power-down current 1.5 a rising slope iout = 10ma 0.3 ms/v line regulation vbat [2.7, 5.5v] 5 mv load regulation iout [0.1, 150ma] 10 mv line transient (1) vdig = 1.2v iout = 150ma vbat = 300mv tr = tf = 10s 1mv load transient (1) vdig = 1.2v iout = [1, 150ma] tr = tf = 1s 40 mv table 13. vana2/3/4 electrical characteristics (continued) parameter name condition min. typ. max. unit
electrical characteristics stw4511 28/46 3.2.3 dc/dc converter monitoring characteristics 3.3 digital specification all electrical specifications using vddio voltage as reference are able to sustain 1.8 v 5%. 3.3.1 cmos input/output static characteristics: i2c interface table 15. vsdc1/2 monitoring output levels symbol description test conditions min. typ. max. units threshold t hcore threshold vsdc1 vsdc1 = 1.2v or 1.5v -3% vsdc1-150 +3% mv vsdc1 = 1v -3% vsdc1-100 +3% mv t hvio threshold vsdc2 -3% 1.65 +3% v table 16. cmos input/output static characteristics: i2c interface symbol description test condition min. typ. max. unit i2c interface vil low level input voltage 0.3xvio v vih high level input voltage 0.7xvio v iil low level input current -1.0 +1.0 a iih high level input current -1.0 +1.0 a vol low level output voltage iol = 3ma (with open drain or open collector) 0.2xvio v voh high level output voltage iol = 3ma (with open drain or open collector) 0.8xvio v
stw4511 electrical characteristics 29/46 3.3.2 cmos input/output dynamic characteristics: i2c interface 1. cb = total capacitance of one bus line in pf 3.3.3 cmos input/output static characteristics: vddio level table 17. cmos input/output dynamic characteristics: i2c interface symbol description min. typ. max. unit i2c interface fscl clock frequency 400 khz thigh clock pulse width high 600 ns tlow clock pulse width low 1300 ns tr sda, scl rise time 20+0.1cb (1) 300 ns tf sda, scl rise time 20+0.1cb (1) 300 ns thd_sta start condition hold time 600 ns tsu_sta start condition set up time 600 ns thd_dat data input hold time 0 ns tsu_dat data input set up time 100 ns tsu_sto stop condition set up time 600 ns tbuf bus free time 1300 ns cb capacitive load for each bus line 400 pf table 18. vddio level: control i/os symbol description test condition min. typ. max. unit sw_reset, vddok, res_pro, pwren vil low level input voltage 0.3xvio v vih high level input voltage 0.7xvio v iil low level input current -1.0 1.5 a iih high level input current -1.0 1.5 a cin input capacitance 10 pf vol low level output voltage iol = 4ma 0.2xvio v voh high level output voltage iol = 4ma 0.8xvio v tof output fall time 1 ns tor input fall time 1 ns ci/o driving capability 100 pf
electrical characteristics stw4511 30/46 3.3.4 cmos input static ch aracteristics: vbat level 3.3.5 nmos input pon table 19. cmos input static characteristics: vbat level symbol description test condition min. typ. max. unit vana2_sel[0:1], vana3_sel[0:1], vana4_sel[0:1], vbat_min_thr_[0,1], vbat_max_thr_[0,1], vram_sel, vbat_thr_sel vil low level input voltage 0.3xvbat v vih high level input voltage 0.7xvbat v iil low level input current -1.0 1.5 a iih high level input current -1.0 1.5 a cin input capacitance 10 pf table 20. pon input static characteristics symbol description test condition min. typ. max. unit pon vil low level input voltage 0.5 v vih high level input voltage 1 vbat v iil low level input current -1.0 1.5 a iih high level input current -1.0 1.5 a
stw4511 i2c interface 31/46 4 i2c interface the i2c interface is used to control the power supplies. the i2c bus is configured as a slave serial interface compatible with the i2c register trademark of philips inc (version 2.1). the device is a slave serial interface with a data line (sda) and a clock line (scl): scl is the input clock used to shift the data, sda is the input/output bidirectional data transfer line. the internal bus connection is composed of: one filter to reject spike on the bus data line and preserve data integrity, one bidirectional data transfer up to 400 kbit/s (fast mode) via sda signal. the sda signal contains the input/output control and data signals that are shifted in the device msb first. the first bit must be high (start) followed by the device id (7 bits). a read/write bit control '1? indicates read access while a logical ?0? indicates a write access. device id: device id in write mode: 5ch device id in read mode: 5dh the device sends an acknowledge at the end of an 8-bit transfer. the following 8-bit sequence corresponds to the register address followed by another acknowledge. the 8-bit data field is sent last and is also followed by a last acknowledge. table 21. device id bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adrd6 adrd5 adrd4 adrd3 adrd2 adrd1 adrd0 r/w table 22. register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 regadr7 regadr6 regadr5 regadr4 regadr3 regadr2 regadr1 regadr0 table 23. register data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0
i2c interface stw4511 32/46 figure 7. control interface: i2c format figure 8. control interface: i2c timing note: multi-write possibility is not available. for each data it is mandatory to send the address first. device address 0 1 0 1 1 1 0 0 regn address regn data in write single byte start ack ack ack stop device address 0 1 0 1 1 1 0 0 regn address start ack ack device address 0 1 0 1 1 1 0 1 regn data out start ack no ack random addr single byte read device address 0 1 0 1 1 1 0 0 regn address start ack ack device address 0 1 0 1 1 1 0 1 start reg n data out ack no ack stop m+1 data bytes ack reg n + m data out random addr multi byte read ack stop start repeated stop t buf t hd_sta t f t low t r t high t hd_dat t su_dat start sda scl t su_sta t hd_sta t su_sto usbsda usbscl
stw4511 clock management 33/46 5 clock management 5.1 internal oscillator the device functions with internal clock at around 1 mhz to switch the step-down converters. this oscillator is operational as soon as pon = 1. 5.2 internal 32 khz clock the device state machine functions with a 32 khz clock generated internally by dividing the internal oscillator frequency.
application hints stw4511 34/46 6 application hints 6.1 application and external components the application diagram shown in figure 9 illustrates an example where ldo is at 3.3 v and the battery supervisor threshold is respectively at 2.85 v and 3.5 v voltage values. vram is supplied by vsdc2 dc/dc converter at 1.8 v. figure 9. application diagram example
stw4511 application hints 35/46 note: the production dispersion, temperature range, biasing and aging must be considered for all the above-listed components. table 24. list of materials name typ. units comments l1 and l2 4.7 h vsdc1 and vsdc2 coils c7 and c10 22 f vsdc1 and vsdc2 output capacitors, x5r type c8 and c9 10 f vsdc1 and vsdc2 input capacitors, x5r type c1, c2, c3, c4, c5 2.2 f ldo output capacitors c15, c16, c17, c18 1 f ldo input capacitors c6 2.2 f vref capacitor c19 10 f vddio bypass capacitor c20 1 f analog supply bypass capacitor c21 20 f dram memory maximum decoupling capacitor value r5 and r6 2.2 k i2c pull-up resistors
register definition and mapping stw4511 36/46 7 register definition and mapping the set of registers used to program the device are accessible via the 5ch i2c address. note: register 1fh must be sent to the i2c before the register 1eh (msb address must be sent first). table 25. register general information address type comment 00h, 01h, 02h reserved 03h r device version id 10h r/w application control register 1 11h r/w application control register 2 12h to 1dh test registers 1eh to 1fh r/w power control registers table 26. register summary register addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device version id 03h01000001 application control register 1 10h reserved pdn_vana2 reserved application register 2 11h pdn_vana1 reserved monitoring_vsdc1/2 0 pdn_vana3 ship_mode reserved pdn_vana4 register15141312109876543210 power control reserved reg_address_2bit reg_address_3bit data_in/out_4bit en address 1fh 1eh
stw4511 register definition and mapping 37/46 application controls register 1 @ 10h address: 10h type: r/w reset: 0000_0000 description: application controls register 2 @ 11h address: 11h type: rw reset: 0000 0000 description: 76543210 reserved pdn_vana2 reserved [7:2] reserved [1] pdn_vana2 0: vana2 in power off (default) 1: vana2 in hpm [0] reserved 76543210 pdn_vana1 reserved monitoring_vsdc1/2 reserved pdn_vana3 ship_mode reserved pdn_vana4 rw r r (1) 1. will be reset after reading rrw [7] pdn_vana1 0: vana1 in power down mode (default) 1: vana1 in high power mode [6] reserved [5] monitoring_vsdc1/2 0: output in the good range (default) 1: output lower than expected on vsdc1 or vsdc2 [4] reserved [3] pdn_vana3 0 : vana3 in power down mode (default) 1 : vana3 in high power mode
register definition and mapping stw4511 38/46 power control register @ 1eh address: 1eh type: rw reset: 0000 0000 description: power control register @ 1fh address: 1fh type: rw reset: 0000 0000 description: [2] ship_mode 0 : no impact (default value) 1 : shipping mode selection : internal switch is off whatever the status of the vram_sel pin [1] reserved [0] pdn_vana4 0: vana4 in power down mode (default) 1: vana4 in high power mode 76543210 register_address_3bit data_in_out_4bit en [7:5] register_address_3bit see ?address? column (lsb) table (default =0) [4:1] data_in_out_4bit see control register table (default = 0) [0] en 0: read enabled (default) 1: write enabled 1514131211109876543210 reserved reg_address_2bit reserved [15:8] reserved [9:8] reg_address_2bit see ?address? column (msb) table (default = 0)
stw4511 register definition and mapping 39/46 power control register mapping power control register @ 05h address: 05h type: rw reset: 0000 0000 1011 1100 description: table 27. power control register mapping address 1fh address 1eh comment reserved reg_address data_in/out en 2-bit msb 3-bit lsb 151413121110987654321 0 00h to 04h test purpose 05h to 09h setting power control register @ 05h to power control register @ 09h 0bh to 1eh test purpose address 1fh address 1eh 1514131211109876543210 reserved 0 0 1 0 1 vsdc1_vdig[3:0] en [15:10] reserved [4:1] vsdc1_vdig_prg[3:0] 0000 1.00 v 0001 = 1.05 v 0010 1.10 v 0011 1.15 v 0100 1.20 v 0101 1.22 v 0110 1.24 v 0111 1.26 v 1000 1.28 v 1001 1.30 v 1010 1.32 v 1011 1.40v 1100 1.43 v 1101 1.45 v (default) 1110 1.47 v 1111 1.50 v [0] en 0 read enabled (default) 1 write enabled
register definition and mapping stw4511 40/46 power control register @ 06h address: 06h type: rw reset: 0000 0000 1101 1110 description: power control register @ 07h address: 07h type: rw reset: 0000 0000 1111 0110 description: address 1fh address 1eh 1514131211109876543210 reserved 0 0 1 1 0 1 en_vdig 1 1 en rrrrrrw [15:10] reserved [4] 1 default value = 1 [3] en_vdig 0: vdig in power down mode 1: vdig in high power mode (default) [2] 1 default value = 1 [1] 1 default value = 1 [0] en 0: read enabled (default) 1: write enabled address 1fh address 1eh 1514131211109876543210 reserved 0 0 1 1 1 en_vana3 reserved en_vana4 reserved en r rrrrrrwrrwrrw [15:10] reserved [4] en_vana3 0: vana3 in power down mode 1: vana3 in high power mode (default) [3] reserved
stw4511 register definition and mapping 41/46 power control register @ 08h address: 08h type: rw reset: 0000 0001 0000 1100 description: [2] en_vana4 0: vana4 in power down mode 1: vana4 in high power mode (default) [1] reserved [0] en 0: read enabled (default) 1: write enabled address 1fh address 1eh 1514131211109876543210 reserved 0 1 0 0 0 reserved en_monitoring en_vana2 reserved en r rrrrrrrrwrrw [15:10] reserved [4] reserved [3] en_monitoring 0: disabled/monitoring = off 1: enabled/vsdc1 and vsdc2 monitoring = 0n (default) [2] en_vana2 0: vana2 in power down mode 1: vana2 enabled in high power mode (default) [1] reserved [0] en 0: read enabled (default) 1: write enabled
register definition and mapping stw4511 42/46 power control register @ 09h address: 09h type: rw reset: 0000 0001 0011 1010 description: address 1fh address 1eh 1514131211109876543210 reserved 0 1 0 0 1 vana2/3_off 0 reserved vana4_off en r rrrrrrwrrwrrw [15:10] reserved [9] 0: default value = 0 [8] 1: default value = 1 [7] 0: default value = 0 [6] 0: default value = 0 [5] 1: default value = 1 [4] vana2_vana3_off: when pwren = 0 0: vana2 and vana3 stay in hpm 1: vana2 and vana3 go in off mode (default) [3] 0: default value = 0 [2] reserved [1] vana4_off: when pwren = 0 0: vana4 stay in hpm 1: vana4 go in off mode (default) [0] en 0: read enabled (default) 1: write enabled
stw4511 package mechanical data 43/46 8 package mechanical data table 28. tfbga 6mm x 6mm x 1.2mm with 0.5 mm pitch and 0.3 mm ball databook (mm) drawing (mm) ref. min. typ. max. min. typ. max. a (1) 1. tfbga stands for thin profile fine pitch ball grid array. thin profile: the total profile height (dim a) is measured fr om the seating plane to the top of the component. the maximum total package height is calculated by the following methodology: 1.20 1.06 a1 0.15 0.16 0.21 0.26 a2 0.20 0.16 0.20 0.24 a4 0.585 0.57 0.585 0.60 b (2) 2. the typical hall diameter before mounting is 0.30mm. 0.25 0.30 0.35 0.25 0.30 0.35 d 5.85 6.00 6.15 5.90 6.00 6.10 d1 4.50 4.50 e 5.85 6.00 6.15 5.90 6.00 6.10 e1 4.50 4.50 e 0.50 0.50 z 0.75 0.75 ddd 0.08 0.08 eee (3) 3. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindric al tolerance zone eee perpendicular to datum c and located on true position with respect to datums a and b as defined by e. the axis perpendicular to datum c of each bail must lie within this tolerance zone. 0.15 0.15 fff (4) 4. the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is contained entirely in the respective zone eee above. the axis of each ball must lie simultaneously in both tolerance zones. 0.05 0.05 1.00mm a 1.20mm/fine pitch: e 1.00mm pitch. < < a max a1 typa2 typa4 typ a1 2 a2 2 a3 2 tolerance values ++ () +++ =
package mechanical data stw4511 44/46 figure 10. tfbga 6mm x 6mm x 1.2mm with 0.5 mm pitch and 0.3 mm ball 1. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of eac h corner is optional. see note 1
stw4511 ordering information 45/46 9 ordering information 10 revision history table 29. ordering information order code package packing stw4511bh)/hf tfbga 6mm x 6mm x 1.2mm tray stw4511bh)t/hf tfbga 6mm x 6mm x 1.2mm tape and reel table 30. document revision history date revision changes 26-nov-2008 1 initial release. 10-feb-2009 2 updated the minimum temperature value in the section related to absolute maximum ratings. 12-jun-2009 3 added vana3 in the functional description and the register description. added one section on shipping mode in the functional description and the shipping_mode bit in the register description. updated the minimum value for the package rth in the absolute maximum ratings. updated the document status to datasheet with respect to the device maturity level. updated the ordering information.
stw4511 46/46 please read carefully: the contents of this document are subject to change without prior notice. st-ericsson makes no representation or warranty of an y nature whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to warranties of merchantability or fitness for a particular purpose, interpretability or interoperability or, against infringement of third par ty intellectual property rights, and in no event shall st-ericsson be liable to any part y for any direct, indirect, incidental and or consequential dama ges and or loss whatsoever (including but not limited to monetary losses or loss of data), that might arise from the use of this document or th e information in it. st-ericsson and the st-ericsson logo are trademarks of the st-ericsson group of companies or used under a license from stmicroelectronics nv or telefonaktiebolaget lm ericsson. all other names are the property of their respective owners. ? st-ericsson, 2009 - all rights reserved contact information at www.stericsson.com under contacts www.stericsson.com

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